1. Field of the Invention
The present invention relates generally to the design of a counter. In particular, it relates to the design of an asynchronous ping-pong counter.
2. Description of the Background Art
A counter is defined here as a building block that receives a fast clock and a slow clock, and generate an output value. A rising edge is defined as the transition of a digital signal from low to high. The output value represents the number of rising edges of the fast clock that exists between two neighboring rising edges of the slow clock. A synchronous counter clocked by the fast clock can be used to over-sample the slow clock to determine the number of rising edges by inspecting the sampled results. However, if the fast clock runs at a very high speed, e.g. 5 GHz, and the slow clock runs at an extremely slow speed, e.g. 10 MHz, it is almost impossible to meet both the setup and hold timing requirements of each flip-flop by using any synchronous counter in existing technologies. An asynchronous ping-pong counter is presented in this work to solve the aforementioned problems.